Superscalar
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A superscalar CPU architecture implements a form of parallelism called Instruction level parallelism within a single processor. It thereby allows faster CPU throughput than would otherwise be possible at the same clock rate. A superscalar architecture executes more than one instruction during a single pipeline stage by pre-fetching multiple instructions and simultaneously dispatching them to redundant functional units on the processor. The superscalar approach is but one performance enhancing method based on exploiting instruction level parallelism.
Superscalar processors differ from multi-core processors in that the redundant functional units are not entire processors. A single processor is composed of finer-grained functional units such as the ALU, integer multiplier, integer shifter, floating point unit, etc. On a superscalar design there may be multiple versions of each functional unit which can simultaneously be harnessed to process instructions concurrently. The two approaches are not mutually exclusive, and each CPU on a multiple-core chip may be of superscalar design.
The simplest processors are scalar processors. A scalar processor processes one data item at a time. In a vector processor, by contrast, a single instruction operates simultaneously on multiple data items. The difference is analogous to the difference between scalar and vector arithmetic. A superscalar processor is sort of a mixture of the two. Each instruction processes one data item, but there are multiple redundant functional units within each CPU so that multiple instructions can be processing separate data items concurrently.
A superscalar processor usually sustains an execution rate in excess of one instruction per machine cycle. But merely processing multiple instructions concurrently does not make an architecture superscalar. A pipelined CPU typically loads an instruction while doing arithmetic for the previous one and storing the results from the one before that (thus executing 3 instructions at the same time) -- but simple pipelining alone sustains (at best) one instruction per machine cycle, and is therefore not superscalar processing.
In a superscalar CPU the dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to the redundant functional units within a single CPU.
Available performance improvement from superscalar techniques is limited by two key areas: (1) The degree of intrinsic parallelism in the instruction stream, and (2) The complexity and time cost of the dispatcher and associated dependency checking logic.
Existing binary executable programs have varying degrees of intrinsic parallelism. In some cases instructions are not dependent on each other and can be executed simultaneously. In other cases they are inter-dependent: one instruction impacts either resources or results of the other. The instructions a = b + c; d = e + f can be run in parallel because none of the results depend on other calculations. However, the instructions a = b + c; d = a + f might not be runable in parallel, depending on the order in which the instructions complete as they move through the units.
As the number of simultaneously issued instructions increases, the cost of dependency checking increases extremely rapidly. This is exacerbated by the need to check dependencies at run time and at the CPU's clock rate. This cost includes additional logic gates required to implement the checks, and time delays through those gates. Research shows the gate cost in some cases may be n^k gates, and the delay cost k^2 log n, where n is the number of instructions in the processor's instruction set, and k is the number of simultaneously dispatched instructions. In mathematics, this is a called a combinatoric problem involving permutations.
Even though the instruction stream may contain no inter-instruction dependencies, a superscalar CPU must nonetheless check for that possibility, as there is no assurance otherwise and failure to detect a dependency would produce incorrect results.
No matter how advanced the semiconductor process or how fast the switching speed, this places a practical limit on how many instructions can be simultaneously dispatched. While process advances will allow ever greater numbers of functional units (e.g, ALUs), the burden of checking instruction dependencies grows so rapidly that the achievable superscalar dispatch limit is fairly small. -- likely on the order of five to six simultaneously dispatched instructions.
However even given infinitely fast dependency checking logic on an otherwise conventional superscalar CPU, if the instruction stream itself has many dependencies, this would also limit the possible speedup. Thus the degree of intrinsic parallelism in the code stream forms a second limitation.
Collectively, these two limits drive investigation into alternative architectural performance increases such as Very Long Instruction Word (VLIW) and multi-core processors .
With VLIW, the burdensome task of dependency checking by hardware logic at run time is removed to the compiler. The checks which in a superscalar design must be completed within nanoseconds can be performed in seconds, and if on a multi-core machine and using a multithreaded compiler, by multiple processors in parallel.
Superscalar CPU design emphasizes improving the instruction dispatcher accuracy, and allowing it to keep the multiple functional units in use at all times. This has become increasingly important as the number of units has increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design like the PowerPC 970 includes four ALUs and two FPUs, as well as two SIMD units. If the dispatcher is ineffective at keeping all of these units fed with instructions, the performance of the system as a whole will suffer.
Seymour Cray's CDC 6600 from 1965 is often mentioned as the first superscalar design. The Intel i960CA (1988) and the AMD 29000-series 29050 (1990) microprocessors were the first commercial single-chip superscalar microprocessors. RISC CPUs like these brought the superscalar concept to micro computers because the RISC design results in a simple core, allowing straightforward instruction dispatch and the inclusion of multiple functional units (such as ALUs) on a single CPU in the constrained design rules of the time. This was the reason that RISC designs were faster than CISC designs through the 1980s and into the 1990s.
Except for CPUs used in some battery-powered devices, essentially all general-purpose CPUs developed since about 1998 are superscalar. Beginning with the "P6" (Pentium Pro and Pentium II) implementation, Intel's 80386 architecture microprocessors have implemented a CISC instruction set on a superscalar RISC micro-architecture. Complex instructions are internally translated to a RISC-like "micro-ops" RISC instruction set, allowing the processor to take advantage of the higher-performance underlying processor while remaining compatible with earlier Intel processors.
[edit] See also
- Super-threading
- Simultaneous multithreading
- Speculative execution / Eager execution
[edit] References
- Mike Johnson, Superscalar Microprocessor Design, Prentice-Hall, 1991, ISBN 0-13-875634-1
- Sorin Cotofana, Stamatis Vassiliadis: On the Design Complexity of the Issue Logic of Superscalar Machines. EUROMICRO 1998: 10277-10284
