Shallow trench isolation
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Shallow Trench Isolation is a design technique for semiconductors.
As the semiconductor industry moves to sub 65 nm levels there is a need for creating very small void free gaps on the wafer sublayer. LOCOS was used before STI came into the picture. The STI creation process could be described as
- oxidation
- deposition
- lithography
- etch
- cleaning process
- fill
- chemical mechanical planarization (CMP)
There also exists an obvious deep trench isolation complementing the shallow trench isolation.
