OpenRISC

From Wikipedia, the free encyclopedia

OpenRISC is an open source hardware RISC CPU design by OpenCores released under the GNU Lesser General Public License. The design is implemented in the verilog hardware description language and has been manufactured successfully as an ASIC as well as being hosted in FPGA environments.

The GNU toolchain has been ported to OpenRISC to support development in several languages and Linux and uClinux have been ported to the processor.

[edit] See also

• LEON
• OpenSPARC
• S1 Core

[edit] External links

• Open Cores Website
• GNU toolchain building guides

This microcomputer/microprocessor-related article is a stub. You can help Wikipedia by expanding it.

This computer hardware-related article is a stub. You can help Wikipedia by expanding it.

Retrieved from "http://en.wikipedia.org../../../o/p/e/OpenRISC_83ad.html"

Categories: Microcomputer stubs | Computer hardware stubs | Open machine

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• This page was last modified 19:23, 12 October 2006 by Anonymous user(s) of Wikipedia. Based on work by Wikipedia user(s) Raysonho, JonHarder, Everyking, Rich Farmbrough, Phoenix-forgotten, Frap, Kglavin, Remuel, DrYak, CanisRufus, Hooperbloob, Honta, Kate, Nixdorf, Flockmeal and Crusadeonilliteracy.
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