Halt and Catch Fire
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This article is based in part on the Jargon File, which is in the public domain.
Halt and Catch Fire, known by the mnemonic HCF, was originally a fictitious computer machine code instruction claimed to be under development at IBM for use in their System/360 computers, along with many other amusing instructions such as "Execute Operator".
In modern practice, HCF denotes an undocumented machine code instructions with unusual side-effects, included in the processor for test purposes. The old "Halt and Catch Fire" instruction and HCF mnemonic were appropriated by users who discovered these instructions as a humorous way of expressing that the unintended execution of such an instruction causes the system to fail to perform its normal functions, while nevertheless appearing quite busy. The expression "catch fire" is strictly metaphorical.
The Motorola 6800 microprocessor was the first for which an HCF opcode became widely known. The instruction makes the processor enter a mode intended for manufacturing testing, in which it continuously performs memory read cycles from successive addresses, with no intervening instruction fetches. Effectively the address bus becomes a counter, allowing the operation of all address lines to be quickly verified. Once the processor has entered this test mode, it is not responsive to interrupts, so normal operation can only be restored by a reset.
There are apocryphal results of damage resulting from the use of such instructions, but there is no documented evidence of such an instruction actually causing damage to a computer. Obviously special instructions designed into a processor for use in manufacturing tests would not be designed in such a manner as to cause damage to that processor.
However, in an embedded system the unintended execution of an HCF instruction could easily cause problems in the system being controlled. For instance, the system could fail to stop a machine when the closure of a limit switch occurs. This problem is not specific to an HCF instruction, and could occur if the software "crashes" for any reason. Properly designed systems have hardware interlocks and watchdog timers to prevent such occurrences or limit their consequences.
