Carry look-ahead adder

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A Carry Look-Ahead Adder is one type of adder used in digital logic. It can be contrasted with the simpler, but usually slower, ripple carry adder (see adder for detail on ripple carry adders). Whereas in a ripple carry adder, each bit of the adder must wait for the carry output from less significant bits, in a carry lookahead adder, all the carry outputs are calculated at once by specialized lookahead logic. The result is that instead of having to wait for the output to "ripple" up to the most significant bit, the entire result can be computed with significantly less delay.

Carry lookahead adders are faster than ripple carry adders, with a couple of caveats. First, the carry lookahead logic can require a significant number of logic gates. In ripple carry adders (and in the individual adder components of a carry lookahead adder), each bit requires a constant number of logic gates. If n is the number of bits in the adder, the number of logic gates is O(n). By contrast, the carry lookahead logic requires O( $n 2$ ) logic gates to implement. In fact, the story is even somewhat worse than this. As n grows, it becomes necessary to use logic gates with more inputs. These larger logic gates require more transistors, and although the number of logic gates is only O( $n 2$ ), the number of transistors is O( $n 3$ ). Therefore, as n grows, the size of a carry lookahead adder can become quite unwieldy. Second, logic gates with a large number of inputs tend to be slower. In addition, above a certain threshold (technology-specific), building logic gates with more inputs is impossible (or at least very impractical). Infeasibly large logic gates can be broken down into multiple stages, but as a result, the delay of the carry lookahead logic is not truly independent of the number of bits (although it still does depend somewhat less on the number of bits than a ripple carry adder). There is a variant that uses shared logic to cut down on transistor count called the Manchester carry chain

In summary, increasing the number of bits in the input of a "pure" carry lookahead adder faces increasing costs, as well as decreasing gains. As a result, in practice it is not rare to see a combination of carry lookahead and ripple carry techiques for large adders. For example, an 8-bit adder may be built from two 4-bit carry lookahead adders, connected in a ripple carry configuration. Another more advanced technique, which can be seen as a natural extension of carry lookahead for binary addition, uses the carry lookahead method on the outputs of smaller adders (which themselves may be carry lookahead adders) to build up a larger result. For example, a 16-bit adder may be implemented as four 4-bit adders, connected in a carry lookahead configuration.

1 Carry lookahead method
2 Demonstration of method
3 Implementation details
4 Manchester carry chain
5 See also
6 References

[edit] Carry lookahead method

Carry lookahead logic uses the concepts of generating and propagating carries. Although in the context of a carry lookahead adder, it is most natural to think of generating and propagating in the context of binary addition, the concepts can be used more generally than this. In the descriptions below, the word digit can be replaced by bit when referring to binary addition.

The addition of two 1-digit inputs A and B is said to generate if the addition will always carry, regardless of whether there is an input carry (equivalently, regardless of whether any less significant digits in the sum carry). For example, in the decimal addition 52 + 67, the addition of the tens digits 5 and 6 generates because the result carries to the hundreds digit regardless of whether the ones digit carries (in the example, the ones digit clearly does not carry).

In the case of binary addition, $A + B$ generates if and only if both A and B are 1. If we write $G (A, B)$ to represent the binary predicate that is true if and only if $A + B$ generates, we have:

G (A, B) = A

and B

The addition of two 1-digit inputs A and B is said to propagate if the addition will carry whenever there is an input carry (equivalently, when the next less significant digit in the sum carries). For example, in the decimal addition 37 + 62, the addition of the tens digits 3 and 6 propagate because the result would carry to the hundreds digit if the ones were to carry (which in this example, it does not). Note that propagate and generate are defined with respect to a single digit of addition and do not depend on any other digits in the sum.

In the case of binary addition, $A + B$ propagates if and only if at least one of A or B is 1. If we write $P (A, B)$ to represent the binary predicate that is true if and only if $A + B$ propagates, we have:

P (A, B) = A

or B

Sometimes a slightly different definition of propagate is used. By this definition A + B is said to propagate if the addition will carry whenever there is an input carry, but will not carry if there is no input carry. It turns out that the way in which generate and propagate bits are used by the carry lookahead logic, it doesn't matter which definition is used. In the case of binary addition, this definition is expressed by:

$P^{\prime}(A,B) = A$ xor B

For binary arithmetic, or is faster than xor and takes less transistors to implement, and therefore $P (A, B)$ is usually used instead of $P^{\prime}(A,B)$ .^{[citation needed]} However, for a multiple-level carry lookahead adder, it is simpler to use $P^{\prime}(A,B)$ .

Given these concepts of generate and propagate, when will a digit of addition carry? It will carry precisely when either the addition generates or the next less significant bit carries and the addition propagates. Written in boolean algebra, with $C i$ the carry bit of digit i, and $P i$ and $G i$ the propagate and generate bits of digit i respectively,

$C_{i+1} = G_i\ \textbf{or}\ (P_i\ \textbf{and}\ C_i)$

[edit] Demonstration of method

Let's try a little experiment. Here is a series of numbers. See how long it takes you to find the most significant digit (the number to the far left).

  3456789876543
+ 6543210123456

The most significant digit is 9. How can we tell? We can look at the far left digits being added. 3 + 6 = 9. If we were to add 1 to this value, the most significant digit would be 1 (9 + 1 = 10). So, we have to look at the digit to the right of this one, to see if there is a carry. Do the same for the following problem:

  3456789876543
+ 6544210123456

You will notice there is 6 + 4, which will generate a carry. Since we know all the sums to the left of this value are 9, we know immediately that the most significant digit will be 1. Try this again for this last example:

  9999919999999
+ 0000090000000

As you can see, we can quickly determine the most significant digit by looking whether the two values sum to 9 (will propagate a carry), or sum greater than 9 (will generate a carry). This is the basic principle behind the Carry Look Ahead adder.

[edit] Implementation details

For each bit in a binary sequence to be added, the Carry Look Ahead Logic will determine whether that bit pair will generate a carry or propagate a carry. This allows the circuit to "pre-process" the two numbers being added to determine the carry ahead of time. Then, when the actual addition is performed, there is no delay from waiting for the ripple carry effect (or time it takes for the carry from the first Full Adder to be passed down to the last Full Adder). Below is a simple 4-bit generalized Carry Look Ahead circuit that combines with the 4-bit Ripple Carry Adder we used above with some slight adjustments:

4-bit Carry Lookahead Adder

For any circuit larger than 4 bits, the Carry Look Ahead circuitry becomes very complicated. For the example provided, the logic for the generate (g) and propagate (p) values are given below. Note that the numeric value determines the signal from the circuit above, starting from 0 on the far left to 3 on the far right:

$C_1 = G_0 + P_0 \cdot C_0$

$C_2 = G_1 + P_1 \cdot C_1$

$C_3 = G_2 + P_2 \cdot C_2$

$C_4 = G_3 + P_3 \cdot C_3$

Substituting $C 1$ into $C 2$ , then $C 2$ into $C 3$ , then $C 3$ into $C 4$ yields the expanded equations:

$C_1 = G_0 + P_0 \cdot C_0$

$C_2 = G_1 + G_0 \cdot P_1 + C_0 \cdot P_0 \cdot P_1$

$C_3 = G_2 + G_1 \cdot P_2 + G_0 \cdot P_1 \cdot P_2 + C_0 \cdot P_0 \cdot P_1 \cdot P_2$

$C_4 = G_3 + G_2 \cdot P_3 + G_1 \cdot P_2 \cdot P_3 + G_0 \cdot P_1 \cdot P_2 \cdot P_3 + C_0 \cdot P_0 \cdot P_1 \cdot P_2 \cdot P_3$

To determine whether a bit pair will generate a carry, the following logic works:

$G_i = A_i \cdot B_i$

To determine whether a bit pair will propagate a carry, either of the following logic statements work:

$P_i = A_i \oplus B_i$

P i = A i + B i

The reason why this works is based on evaluation of $C_1 = G_0 + P_0 \cdot C_0$ . The only difference in the truth tables between ( $A \oplus B$ ) and ( $A + B$ ) is when both $A$ and $B$ are 1. However, if both $A$ and $B$ are 1, then the $G 0$ term is 1 (since its equation is $A \cdot B$ ), and the $P_0 \cdot C_0$ term becomes irrelevant. The XOR is used normally within a basic full adder circuit; the OR is an alternate option (for a carry lookahead only) which is far simpler in transistor-count terms.

The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each CLA Logic circuit produce a propagate and generate signal to a higher-level CLA Logic circuit. The group propagate ( $P G$ ) and group generate ( $G G$ ) for a 4-bit CLA are:

$PG = P_0 \cdot P_1 \cdot P_2 \cdot P_3$

$GG = G_3 + G_2 \cdot P_3 + G_1 \cdot P_3 \cdot P_2 + G_0 \cdot P_3 \cdot P_2 \cdot P_1$

Putting 4 4-bit CLAs together yields four group propagates and four group generates. A Lookahead Carry Unit (LCU) takes these 8 values and uses identical logic to calculate $C i$ in the CLAs. The LCU then generates the carry input for each of the 4 CLAs and a fifth equal to $C 16$ .

The calculation of the gate delay of a 16-bit added (using 4 CLAs and 1 LCU) is not as straight forward as the ripple carry adder. Starting at time of zero:

calculation of $P i$ and $G i$ is done at time 1
calculation of $C i$ is done at time 3
calculation of the $P G$ is done at time 2
calculation of the $G G$ is done at time 3
calculation of the inputs for the CLAs from the LCU are done at
- time 0 for the first CLA
- time 4 for the second CLA
- time 5 for the third & fourth CLA
calculation of the S_i are done at
- time 4 for the first CLA
- time 7 for the second CLA
- time 8 for the third & fourth CLA
calculation of the final carry bit ( $C 16$ ) is done at time 5

The maximum time is 8 gate delays (for $S [8 - 15]$ ). A standard 16-bit ripple carry adder would take 31 gate delays.

[edit] Manchester carry chain

The Manchester carry chain is a variation of the carry look-ahead adder that uses shared logic to lower the transistor count. As can be seen above in the implementation section, the logic for generating each carry contains all of the logic used to generate the previous carries. A Manchester carry chain generates the intermediate carries by tapping off nodes in the gate that calculates the most significant carry value. Not all logic families have these internal nodes, however, CMOS being a major example. Dynamic logic can support shared logic, as can transmission gate logic. One of the major downsides of the Manchester carry chain is that the capacitive load of all of these outputs, together with the resistance of the transistors causes the propagation delay to increase much quicker than a regular carry look-ahead. A Manchester carry chain section generally won't exceed 4 bits.

[edit] See also

[edit] References

Hardware algorithms for arithmetic modules, ARITH research group, Aoki lab., Tohoku University
Katz, Randy (1994). Contemporary Logic Design. The Benjamin/Cummings Publishing Company, 249-256. DOI:10.1016/0026-2692(95)90052-7. ISBN 0-8053-2703-7.

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