45 nanometer

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CMOS manufacturing
processes

1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 45 nanometer (45 nm) process is the next milestone (to be commercially viable in mid 2007 to early 2008) in semiconductor manufacturing and fabrication. Intel is targeting 45 nm production in late 2007, and AMD, IBM, Infineon, Samsung, Chartered Semiconductor, Toshiba, and Sony have completed a common 45 nm process.

Per ITRS, the 45 nm technology node should have significantly tighter specs than the current 65 nm node. '45 nm' itself should refer to the average half-pitch of a memory cell manufactured at that technology level.

While average feature sizes are less than 65 nm, the wavelength of light used is actually 193 nm. A variety of techniques, such as larger lenses, are used to make sub-wavelength features. Double patterning may also be introduced to assist in shrinking distances between features, especially if dry lithography is used.

Intel stated in 2003 that high-k gate dielectrics may be introduced at the 45 nm node to reduce gate leakage current. However, chipmakers have since then voiced concerns about introducing these new materials into the gate stack.

[edit] Technology demos

Intel demonstrated a 0.346 square micrometers 45 nm node SRAM cell in January 2006, a respective 39% and 65% area reduction compared to its previous 65 nm and 90 nm SRAM cell demonstrations (0.57 and 1.0 square micrometers, respectively). However, based on reports at IEDM in the past few years, in going from the 90 nm to 65 nm logic process, the minimum pitch changed only 5%. Minimum pitch does not directly correlate to area, as feature lengths may also shrink, and the overall chip area can be reduced by crowding more transistors at the minimum distance. This also means that logic process technology may not depend so critically on improving the lithography technique (which is really used for reducing the minimum pitch).

In 2004, TSMC demonstrated a 0.296 square micrometer 45 nm SRAM cell.

In April 2006, AMD demonstrated a 0.370 square micrometer 45 nm SRAM cell.

In June 2006, Texas Instruments debuted a 0.24 square micrometer 45 nm SRAM cell, with the help of immersion lithography.

In November 2006, UMC announced that it had developed a 45 nm SRAM chip with a cell size of less than 0.25 square micrometer using immersion lithography and low-k dielectrics.

The successors to 45 nm technology will be 32 nm, 22 nm, and then 16 nm technology per ITRS.