Cyrix 6x86

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Cyrix 6x86是一顆第六代、32位元、x86相容的微處理器，是由Cyrix公司所設計，並由IBM、SGS-Thomson所生產，於1996年發表。

目录 1 架構 2 核心的修訂 3 效能 4 外部連結

[编辑] 架構

6x86在架構設計上結合了RISC與CISC的角度觀點，使其具有一個超純量、超管線的執行核心，並具有暫存器更名（或稱：暫存器重新命名）、猜測執行、亂序執行（也稱：超序執行）、資料相依排除等特性，同時仍可持續原生執行x86指令，這些設計與Centaur公司的WinChip處理器相似，但與Intel公司的Pentium Pro之後，以及AMD公司的K5之後的處理器不同，Intel、AMD的作法已是將CISC指令全面轉化成RISC型態後才加以執行。

With regards to internal caches, it has a 16-kibibyte primary cache and is socket-compatible with the Intel Pentium P54C. It was also unique in that it was the only x86 design to incorporate a 256-byte Level 0 scratchpad cache. It has six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110 MHz, a PR 166+ ran at 133 MHz, etc).

Note that the 6x86 and 6x86L weren't completely compatible with the Intel Pentium instruction set. It is for this reason that by default the chip identified itself as a 80486 and disabled the CPUID instruction. CPUID support could be enabled by first enabling extended CCR registers then setting bit 7 in CCR4. The lack of full Pentium compatibility caused problems with some applications because programmers had begun to use Pentium-specific instructions. Some companies released patches for their products to make them function on the 6x86.

The first generation of 6x86 had heat problems. This was primarily caused by their relatively higher heat output than other CPUs of the day and, as such, computer builders sometimes did not equip them with adequate cooling. The CPUs topped out at around 25 W heat output (like the AMD K6), whereas the Pentium produced around 15 W of waste heat at its peak.

Cyrix 6x86不支援多處理器架構。

[编辑] 核心的修訂

6x86L是Cyrix公司在推出6x86後，針對散熱問題所推出的修訂版，其中「L」的原意是「Low-power，低用電、低功耗」。除此之外更後續的一個發表是6x86MX，主要是加入了MMX多媒體指令集的執行功效，以及加入特有的EMMI指令集，另外也將第一階快取記憶體的記憶容量擴增至64KB，此後也將改名為MII,Cyrux方面認為6x86MX在效能上能與Pentium II處理器競爭，因此才改稱MII。

[编辑] 效能

It has been speculated by experts that 6x86 was designed to perform well specifically on business-oriented benchmarks of the time, most notably Ziff-Davis' Winstone benchmark. [1] Winstone ran various speed tests using several popular applications. It was one of the leading benchmarks during the mid-'90s and was used in some leading magazines, such as Computer Shopper and PC Magazine, as a deciding factor for system ratings.

The 6x86's integer performance was fantastic. As said earlier, Cyrix used a PR rating (Performance Rating) to relate their performance to the Intel Pentium Classic (pre-P55C), because a 6x86 at a lower clock rate outperformed the higher-clocked Pentium. For example, a 133 MHz 6x86 will outperform a Pentium Classic at 166 MHz, and as a result Cyrix could market the 133 MHz chip as being a Pentium 166's equal. A PR rating was also necessary because the 6x86 could not clock as high as Pentium and maintain equivalent manufacturing yields, so it was critical to establish the slower clock speeds as equal in the minds of the consumer. The PR rating was not an entirely truthful representation of the 6x86's performance, however.

While it can be simply said that its integer performance is excellent, the same can not be said with regard to its floating point performance. The FPU is considerably less robust than that of the Pentium (let alone the P6 FPU.) During the 6x86's development, the majority of applications (office software) performed almost entirely integer operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget.

Unfortunately for the competition, Intel wanted to build a more powerful, more workstation-friendly CPU with the Pentium. They built by far their fastest FPU yet; a formidable pipelined unit, the first in an x86 CPU, that could also execute many important FPU instructions very quickly (low latency). Pipelining brought with it the ability to execute more than one instruction per clock cycle, giving it a decisive advantage over chips without a pipelined FPU. The poor FPU performance of the 6x86 can be mostly attributed to major FPU instructions taking at least 4 clocks, putting throughput at one quarter of the Intel P6's peak FPU execution rate. The FPU was not pipelined, and it also was no help that most programmers hand-tailored their code with optimizations designed for the Pentium's FPU. So, while the Pentium was speeding along executing various floating point instructions at a rate of more than one per clock cycle, the 6x86 was executing at a mere fraction of this rate. It was not much faster than a 486 FPU at the same clock speed.

The obvious superiority of the Pentium FPU motivated programmers to push into new areas of the software arts. A powerful FPU was just what was needed for the emerging 3D engines for games. For example, the highly anticipated first person shooter Quake used highly optimized assembly code designed almost entirely around the Pentium's FPU. Fortunately for the 6x86 (and AMD K6), many games continued to be integer-based throughout the chip's lifetime.

6x86的接替者：MII過晚進入市場，同時在運作時脈上也無法拉高。Cyrix已在6x86時代犯下錯誤，與AMD在K5時所犯的錯誤相近，那就是過於專注每單次運作時脈下的整數執行效能表現，勝過於時脈頻率的提升性。因此6x86與MII只能在低階市場中具競爭力，因為後續的AMD K6、Intel Pentium II等一直積極在時脈速度上領先，除這些外，浮點運算單元的效能有限，以及在同價位下整數運算表現也不如新推出的Intel Pentium Pro、AMD K6等，自此在效能上便再也沒有競爭力。

[编辑] 外部連結

• Cyrix 6x86 ("M1") at PCGuide
• cpu-collection.de Cyrix 6x86 processor images and descriptions
• Paul Hsieh's 6th Generation x86 CPU Comparison in-depth analysis of 6th generation x86 CPUs, including the 6x86MX.
• Cyrix M1 stats at Sandpile.org

本文參考素材源自「FOLDOC」，在GFDL下授權。 This article was originally based on material from the Free On-line Dictionary of Computing and is used under the GFDL.