Word (computer science)
From Wikipedia, the free encyclopedia
-
"Word (computing)" redirects here. This article is about the data unit. For the word processor, see Microsoft Word.
In computing, "word" is a term for the natural unit of data used by a particular computer design. A word is simply a fixed-sized group of bits that are handled together by the machine. The number of bits in a word (the word size or word length) is an important characteristic of a computer architecture.
The size of a word is reflected in many aspects of a computer's structure and operation. The majority of the registers in the computer are usually word-sized. The typical numeric value manipulated by the computer is probably word sized. The amount of data transferred between the processing part of the computer and the memory system is most often a word. An address used to designate a location in memory often fits in a word.
Modern computers usually have a word size of 16, 32, or 64 bits. Many other sizes have been used in the past, including 8, 12, 18, 24, 36, 39, 40, 48, and 60 bits; the slab is an example of an early word size. Some of the earliest computers were decimal rather than binary, typically having a word size of 10 or 12 decimal digits, and some early computers had no fixed word length at all.
The most common microprocessors used in personal computers have the x86 architecture (for instance, the Intel Pentiums and AMD Athlons). The x86 family includes several generations of achitecture. In the Intel 8086, 80186, and 80286, the word size is 16 bits. In IA-32, the word size is 32 bits. In x86-64, the word size is 64 bits. Yet each implementation also implements the earlier instruction sets too. So Intel calls 16 bits a word in all of them; clearly this usage of word is different from that of this article.
Contents |
[edit] Uses of words
Depending on how a computer is organized, units of the word size may be used for:
- Integer numbers – Holders for integer numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word-sized holder.
- Floating point numbers – Holders for floating point numerical values are typically either a word or a multiple of a word.
- Addresses – Holders for memory addresses must be of a size capable of expressing the needed range of values, but not be excessively large. Often the size used is that of the word, but it can also be a multiple or fraction of the word size.
- Registers – Processor registers are designed with a size appropriate for the type of data they hold, e.g. integers, floating point numbers, or addresses. Many computer architectures use "general purpose" registers that can hold any of several types of data; those registers are sized to allow the largest of any of those types, and typically that size is the word size of the architecture.
- Memory-processor transfer – When the processor reads from the memory subsystem into a register, or writes a register's value to memory, the amount of data transferred is often a word. In simple memory subsystems, the word is transferred over the memory data bus, which typically has a width of a word or half word. In memory subsystems that use caches, the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the memory hierarchy larger transfers (which are a multiple of the word size) are normally used.
- Unit of address resolution – In a given architecture, successive address values designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).
- Instructions – Machine instructions are normally fractions or multiples of the architecture's word size. This is a natural choice since instructions and data usually share the same memory subsystem. In Harvard architectures the word sizes of instructions and data need not be related.
[edit] Word size choice
When a computer architecture is designed, the choice of a word size is of substantial importance. There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses. However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size. That preferred size becomes the word size of the architecture.
Character size is one of the influences on a choice of word size. Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so alphabetics were limited to upper case. Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines). A common choice then was the 36-bit word, which is also a good size for the numeric properties of a floating point format.
After the introduction of the IBM System/360 design which used eight-bit characters and supported lower-case letters, the standard size of a character (or more accurately, a byte) became eight bits. Word sizes thereafter were naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used.
[edit] Variable word architectures
Early machine designs included some that used what is often termed a variable word length. In this type of organization, a numeric operand had no fixed length but rather its end was detected when a character with a special marking was encountered. Such machines used binary coded decimal for numbers. This class of machines included the IBM 702, IBM 705, IBM 7080, IBM 7010, UNIVAC 1050, IBM 1401, and IBM 1620.
Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory. These machines are often quite slow because of this. For example, instruction fetches on an IBM 1620 Model I take 8 cycles just to read the 12 digits of the instruction (the Model II reduced this to 6 cycles, but reduced the fetch times to 4 cycles if one or 1 cycle if both address fields were not needed by the instruction).
[edit] Word and byte addressing
The memory model of an architecture is strongly influenced by the word size. In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word. In this approach, address values which differ by one designate adjacent memory words. This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally-sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions.
When byte processing is to be a significant part of the workload, it is usually more advantageous to use the byte, rather than the word, as the unit of address resolution. This allows an arbitrary character within a character string to be addressed straightforwardly. A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative. The word size needs to be an integral multiple of the character size in this organization. This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then.
[edit] The power of 2
Data values may occupy differing sizes of memory, because, for instance, some numbers need to be capable of having greater precision than others. The commonly used sizes are usually chosen to be a power of 2 multiple of the unit of address resolution (byte or word). This is convenient because converting the index of an item in an array into the address of the item then requires only a shift operation (which is just a conductor routing in hardware) rather than a multiplication. In some cases this relationship can also avoid the use of division operations. As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of 2 times the size of a byte.
[edit] Size families
As computer designs have grown more complex, the obvious central importance of a single word size to an architecture has decreased. This is due to the more capable hardware making use of a wider variety of sizes of data since differing sizes are most effective in differing contexts. One pressure in this direction is the need to maintain backward compatibility while extending processor capability. As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design.
A major example of this can be seen in the x86 designs. The original 8086 architecture clearly used a word size of 16 bits. The significantly-enhanced design of the 80386 added to the 8086 base an organization which was based around units of 32 bits. If it were an unencumbered design, it would have had a 32-bit word size, but as an extension of the 8086, its word size continued to be considered to be 16 bits. (As a result of this, one hears of the 80386 and successor processors as being "32-bit", but usually not as having a 32-bit word.) This same situation has recently reoccurred in the same line, as the AMD64 architectural extensions bring the 64-bit size into a major position without dropping any of the 16- and 32-bit support.
Thus one sees that today a computer architecture is based on a family of closely related sizes more than on a single omnipresent word size. The sizes are intimately related to one another by integral factors, usually a power of two. Calling any one of them the architecture's word size may be somewhat arbitrary, and a size may be so designated due to the history of the architecture's evolution rather than the properties of the size itself in a recent design.
[edit] Dword and Qword
In computer science, a dword is a unit of data that is double the size of a word and half the size of a qword. On the x86 platform with a wordsize of 16 bits, a dword unit of data would be 32 bits long. To print a dword using printf, fprintf or similar functions use %ld as the designator. In the Microsoft Windows API, a DWORD is a typedef for an unsigned long. To print a DWORD using printf or similar functions use %lu as the designator.
In computer science, a qword (quadruple word) is a unit of data that is twice the size of a dword or four times the size of a word. On the common 32-bit x86 platform, this unit of data would be 64 bits because the size of a Word on an x86 system is 16 bits. On the more recent AMD64/EM64T, which are 64-bit x86 architecture, this unit of data would be 256 bits long, because the Word size on a 64-bit system is 64 bits.
[edit] Table of word sizes
| Year | Computer Architecture |
Word Size w |
Integer Sizes |
Floating Point Sizes |
Instruction Sizes |
Unit of Address Resolution |
Char Size |
|---|---|---|---|---|---|---|---|
| 1941 | Zuse Z3 | 22 b | – | w | 8 b | w | – |
| 1942 | ABC | 50 b | w | – | – | – | – |
| 1944 | Harvard Mark I | 23 d | w | – | 24 b | – | – |
| 1946 (1948) {1953} |
ENIAC (w/Panel #16) {w/Panel #26} |
10 d | w, 2w (w) {w} |
– | – (2d, 4d, 6d, 8d) |
– – {w} |
– |
| 1951 | UNIVAC I | 12 d | w | – | ½w | w | 1 d |
| 1952 | IAS machine | 40 b | w | – | ½w | w | 5 b |
| 1952 | IBM 701 | 36 b | ½w, w | – | ½w | ½w, w | 6 b |
| 1952 | UNIVAC 60 | n d | 1d, ... 10d | – | – | – | 2d, 3d |
| 1953 | IBM 702 | n d | 0d, ... 511d | – | 5d | d | 1 d |
| 1953 | UNIVAC 120 | n d | 1d, ... 10d | – | – | – | 2d, 3d |
| 1954 (1955) |
IBM 650 (w/IBM 653) |
10 d | w | – (w) |
w | w | 2 d |
| 1954 | IBM 704 | 36 b | w | w | w | w | 6 b |
| 1954 | IBM 705 | n d | 0d, ... 255d | – | 5d | d | 1 d |
| 1956 | IBM 305 | n d | 1d, ... 100d | – | 10d | d | 1 d |
| 1958 | UNIVAC II | 12 d | w | – | ½w | w | 1 d |
| 1958 | SAGE | 32 b | ½w | – | w | w | 6 b |
| 1958 | Autonetics Recomp II | 40 b | w, 79 b, 8d, 15d | 2w | ½w | ½w, w | 5 b |
| 1959 | IBM 1401 | n d | 1d, ... | – | d, 2d, 4d, 5d, 7d, 8d | d | 1 d |
| 1959 (TBD) |
IBM 1620 | n d | 2d, ... | – (4d, ... 102d) |
12d | d | 2 d |
| 1960 | LARC | 12 d | w, 2w | w, 2w | w | w | 2 d |
| 1960 | IBM 1410 | n d | 1d, ... | – | d, 2d, 6d, 7d, 11d, 12d | d | 1 d |
| 1960 | IBM 7070 | 10 d | w | w | w | w, d | 2 d |
| 1960 | PDP-1 | 18 b | w | – | w | w | 6 b |
| 1961 | IBM 7030 (Stretch) |
64 b | 1b, ... 64b, 1d, ... 16d |
w | ½w, w | b, ½w, w | 1 b, ... 8 b |
| 1961 | IBM 7080 | n d | 0d, ... 255d | – | 5d | d | 1 d |
| 1962 | UNIVAC III | 25 b, 6 d | w, 2w, 3w, 4w | – | w | w | 6 b |
| 1962 | UNIVAC 1107 | 36 b | 1/6w, ⅓w, ½w, w | w | w | w | 6 b |
| 1962 | IBM 7010 | n d | 1d, ... | – | d, 2d, 6d, 7d, 11d, 12d | d | 1 d |
| 1962 | IBM 7094 | 36 b | w | w, 2w | w | w | 6 b |
| 1963 | Gemini Guidance Computer | 39 b | 26 b | – | 13 b | 13 b, 26 b | – |
| 1963 (1966) |
Apollo Guidance Computer | 15 b | w | – | w, 2w | w | – |
| 1964 | CDC 6600 | 60 b | w | w | ¼w, ½w | w | 6 b |
| 1965 | IBM 360 | 32 b | ½w, w, 1d, ... 16d |
w, 2w | ½w, w, 1½w | 8 b | 8 b |
| 1965 | UNIVAC 1108 | 36 b | 1/6w, ¼w, ⅓w, ½w, w, 2w | w, 2w | w | w | 6 b, 9 b |
| 1965 | PDP-8 | 12 b | w | – | w | w | 8 b |
| 1970 | PDP-11 | 16 b | w | 2w, 4w | w, 2w, 3w | 8 b | 8 b |
| 1971 | Intel 4004 | 4 b | w, d | – | 2w, 4w | w | – |
| 1972 | Intel 8008 | 8 b | w, 2d | – | w, 2w, 3w | w | 8 b |
| 1974 | Intel 8080 | 8 b | w, 2w, 2d | – | w, 2w, 3w | w | 8 b |
| 1975 | Cray-1 | 64 b | 24 b, w | w | ¼w, ½w | w | 8 b |
| 1975 | Motorola 6800 | 8 b | w, 2d | – | w, 2w, 3w | w | 8 b |
| 1975 | MOS Tech. 6501 MOS Tech. 6502 |
8 b | w, 2d | – | w, 2w, 3w | w | 8 b |
| 1976 | Zilog Z80 | 8 b | w, 2w, 2d | – | w, 2w, 3w, 4w, 5w | w | 8 b |
| 1978 (1980) |
Intel 8086 (w/Intel 8087) |
16 b | ½w, w, 2d (w, 2w, 4w) |
– (2w, 4w, 5w, 17d) |
½w, w, ... 7w | 8 b | 8 b |
| 1978 | VAX-11/780 | 32 b | ¼w, ½w, w, 1d, ... 31d, 1b, ... 32b | w, 2w | ¼w, ... 14¼w | 8 b | 8 b |
| 1979 | Motorola 68000 | 32 b | ¼w, ½w, w, 2d | – | ½w, w, ... 7½w | 8 b | 8 b |
| 1982 (1983) |
Motorola 68020 (w/Motorola 68881) |
32 b | ¼w, ½w, w, 2d | – (w, 2w, 2½w) |
½w, w, ... 7½w | 8 b | 8 b |
| 1985 | ARM1 | 32 b | w | – | w | 8 b | 8 b |
| 1985 | MIPS | 32 b | ¼w, ½w, w | w, 2w | w | 8 b | 8 b |
| 1989 | Intel 80486 | 16 b | ½w, w, 2d w, 2w, 4w |
2w, 4w, 5w, 17d | ½w, w, ... 7w | 8 b | 8 b |
| 1989 | Motorola 68040 | 32 b | ¼w, ½w, w, 2d | w, 2w, 2½w | ½w, w, ... 7½w | 8 b | 8 b |
| 1991 | PowerPC | 32 b | ¼w, ½w, w | w, 2w | w | 8 b | 8 b |
| 2000 | Itanium (IA-64) | 64 b | 8 b, ¼w, ½w, w | ½w, w | 41 b | 8 b | 8 b |
| 2002 | XScale | 32 b | w | w, 2w | ½w, w | 8 b | 8 b |
| key: b: bits, d: decimal digits, w: word size of architecture, n: variable size | |||||||
[edit] See also
[edit] References
- Gerrit A. Blaauw & Frederick P. Brooks, Computer Architecture: Concepts and Evolution (Addison-Wesley, 1997, ISBN 0-201-10557-8)
- Anthony Ralston & Edwin D. Reilly, Encyclopedia of Computer Science Third Edition (Van Nostrand Reinhold, 1993, ISBN 0-442-27679-5)
