Delay-locked loop
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In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), with the main difference being the absence of an internal oscillator. A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits (such as DRAM devices). From the outside, a DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit.
The main component of a DLL is a delay chain composed of many delay gates connected back-to-back. The input of the chain (and thus of the DLL) is connected to the clock that is to be negatively delayed. A multiplexer is connected to each stage of the delay chain; the selector of this multiplexer is automatically updated by a control circuit to produce the negative delay effect. The output of the DLL is the resulting, negatively delayed clock signal.
The phase shift can be specified either in constant terms (in delay chain gate units), or as a proportion of the clock period, or both.
Compared to phase-locked loops, delay-locked loops are a relatively recent innovation, first popularized by Xilinx in their Virtex family of FPGA products.[1]
[edit] References
- ^ Kirk, Bob (2001-03-28). "Clock Management with PLLs and DLLs". EETimes.com. Retrieved on 2006-11-11.
